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Connectivity line devices: reset and clock control (RCC)
RM0008
7.3.8
APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DAC
PWR
BKP
CAN2
CAN1
I2C2
I2C1
UART5E
UART4
USART
USART
Reserved
EN
EN
EN
EN
EN
Reserved
EN
EN
N
EN
3EN
2EN
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI3
SPI2
WWD
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
EN
rw
EN
rw
Reserved
GEN
rw
Reserved
EN
rw
EN
rw
EN
rw
EN
rw
EN
rw
EN
rw
Bits 31:30
Reserved, always read as 0.
Bit 29 DACEN : DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN : Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 BKPEN : Backup interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26 CAN2EN : CAN2 clock enable
Set and cleared by software.
0: CAN2 clock disabled
1: CAN2 clock enabled
Bit 25 CAN1EN : CAN1 clock enable
Set and cleared by software.
0: CAN1 clock disabled
1: CAN1 clock enabled
Bits 24:23
Reserved, always read as 0.
Bit 22 I2C2EN : I2C 2 clock enable
Set and cleared by software.
0: I2C 2 clock disabled
1: I2C 2 clock enabled
128/995
Doc ID 13902 Rev 9
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